Micrel
Figure 3 illustrates the CAGC pin interface circuit. The
AGC control voltage is developed as an integrated current
into a capacitor CAGC. The attack current is nominally
7μA, while the decay current is a 10 times scaling of this,
approximately 85μA. Signal gain of the RF/IF strip inside
the IC diminishes as the voltage on CAGC decreases. By
simply adding a capacitor to CAGC pin, the attack/decay
time constant ratio is fixed at 10:1. Modification of the
attack/decay ratio is possible by adding resistance from the
CAGC pin to either VDDBB or VSSBB, as desired.
Both the push and pull current sources are disabled during
shutdown, which maintains the voltage across CAGC, and
improves recovery time in duty-cycled applications. To
further improve duty-cycle recovery, both push and pull
currents are increased by 2 times for approximately 10ms
after release of the SHUT pin. This allows rapid recovery of
any voltage droop on CAGC while in shutdown.
DO Pin
The output stage for the digital output (DO) is shown in
Figure 4. The output is a 45μA push and 45μA pull
switched-current stage. This output stage is capable of
Figure 5. REFOSC Pin
SEL0, SEL1, SWEN, and SHUT Pins
MICRF009
driving
CMOS
loads.
An external buffer-driver
is
recommended for driving high capacitance loads.
Figure 6a. SEL0/SEL1/SWEN Pins
Figure 6b. SHUT Pin
Control input circuitry is shown in Figure 6a and 6b. The
Figure 4. DO Pin
REFOSC1 and REFOSC2 Pin
The REFOSC input circuit is shown in Figure 5. Input
impedance is quite high (200k ? ). This is a Colpitts
oscillator, with internal 10pF capacitors. This input is
intended to work with standard crystal resonators,
connected from this pin to REFOSC2.
This REFOSC2 pin appears as a low resistance path to
VSS during normal operation and is an input to a buffer
amplifier used during the initial start up phase to ensure
rapid build up of crystal oscillations.
The resonators should not contain integral capacitors,
since these capacitors are contained inside the IC.
standard input is a logic inverter constructed with minimum
geometry MOSFETs (Q2, Q3). P-Channel MOSFET Q1 is
a large channel length device, which functions essentially
as a “weak” pull-up to VDDBB. Typical pull-up current is
5μA, leading to an impedance to the VDDBB supply of
typically 1M ? .
Externally
applied
signals
should
be AC-coupled,
amplitude limited to approximately 0.5V PP . The nominal
DC bias voltage on this pin is 1.4V
January 18, 2005
11
M9999-011805
(408) 955-1690
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